Field effect transistors (FET's) and particularly Metal-Oxide-Semiconductor field effect transistors (MOSFETs) are the dominant electronic devices in use today. The performance of these devices has been improved steadily through the reduction in device dimensions, from 10–20 μm channel length in the '70 to 100 nm channel length in '00 technology.
As the channel length becomes smaller than 100 nm, MOSFET devices experience certain deleterious performance due to their size, such as the short channel effect caused by the close proximity of the source and drain, resulting in the reduction of the threshold voltage and the increase of sub-threshold current. With a short channel length, the source and drain regions may extend towards each other and may essentially occupy the entire channel area between the source and the drain. As a result of this effective occupation of the channel area by the source and drain, the channel is in part depleted and the gate charge necessary to alter the source and drain current flow is reduced. Thus the interaction between the source and drain of the MOSFET degrades the ability of the gate to control the operation of the device.
Therefore, scaling of conventional bulk MOSFET devices beyond the 50 nm process generations is very difficult. Straightforward scaling requires ultra thin gate dielectric (equivalent oxide thickness should be less than 0.5 nm), ultra shallow junction (less than 10 nm depth for reducing short channel effect) and high concentration channel doping (>1018 cm−3), all of which generate different problems of similar magnitude. For example, ultra thin gate oxide (less than 1–2 nm) has significant problem of tunneling current, and ultra shallow junction has significant problem of low sheet resistance and junction lateral steepness.
Significant innovations have been made to the conventional bulk MOSFET devices to improve their performance. Silicon-On-Insulator (SOI) substrate has enabled MOSFET devices to have higher speed, lower power and higher density. Strain-induced band modification of the device channel has enabled MOSFET devices to have enhanced carrier mobility and therefore increased drive current. Double gate MOSFET structure allows gate control of the channel from both sides, reducing short channel effect and allowing more current flow.
SOI wafers improve the transistor performance by reducing the operating silicon volume and by isolating the transistors. The thin surface silicon layer limits the volume of silicon that needs to be charged to switch the transistor on and off, and therefore reduces the parasitic capacitance of the transistor and increases the switching speed. The insulating layer isolates the transistor from its neighbors, and therefore reduces the leakage current and allows the transistor to operate at lower supply voltages and thus the transistors can be smaller and more densely packed.
Further improvement of the MOSFET device performance is the introduction of strain-induced band modification of the device channel. Generally speaking, a compressive strained channel MOSFET has significant hole mobility enhancement, and a tensile strained channel MOSFET achieves both significant hole and electron mobility enhancement. Enhanced carrier mobility allows strained silicon MOSFET devices to exhibit vastly increased performance over their bulk silicon counterparts at identical gate lengths.
Double gate MOSFET structure offers improvement for short channel effect reduction since it adds another gate on either side of the channel to allow gate control of the channel from both sides. Additionally, when the device is turned on using both gates, two conduction layers are formed, allowing more current flow. An extension of the double gate is the wrap-around gate where the gate is surrounding the channel. One variation of double gate MOSFET structure is finFET, a double gate device consists of a silicon channel formed in a silicon vertical fin controlled by a self-aligned double gate.